161 lines
4.6 KiB
C
161 lines
4.6 KiB
C
/**************************************************************************//**
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* @file cmsis_armclang_r.h
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* @brief CMSIS compiler armclang (Arm Compiler 6) header file
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* @version V6.0.0
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* @date 04. December 2024
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******************************************************************************/
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/*
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* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_ARMCLANG_R_H
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#define __CMSIS_ARMCLANG_R_H
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#pragma clang system_header /* treat file as system include file */
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#ifndef __CMSIS_ARMCLANG_H
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#error "This file must not be included directly"
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/** \brief Get CPSR Register
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\return CPSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
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{
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uint32_t result;
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__ASM volatile("MRS %0, cpsr" : "=r" (result) );
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return(result);
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}
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/** \brief Set CPSR Register
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\param [in] cpsr CPSR value to set
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*/
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__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
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{
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__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
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}
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/** \brief Get Mode
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\return Processor Mode
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*/
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__STATIC_FORCEINLINE uint32_t __get_mode(void)
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{
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return (__get_CPSR() & 0x1FU);
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}
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/** \brief Set Mode
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\param [in] mode Mode value to set
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*/
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__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
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{
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__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
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}
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/** \brief Get Stack Pointer
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\return Stack Pointer value
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*/
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__STATIC_FORCEINLINE uint32_t __get_SP(void)
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{
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uint32_t result;
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__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
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return result;
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}
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/** \brief Set Stack Pointer
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\param [in] stack Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
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{
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__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
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}
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/** \brief Get USR/SYS Stack Pointer
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\return USR/SYS Stack Pointer value
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*/
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__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
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{
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uint32_t cpsr;
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uint32_t result;
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__ASM volatile(
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV %1, sp \n"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
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);
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return result;
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}
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/** \brief Set USR/SYS Stack Pointer
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
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{
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uint32_t cpsr;
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__ASM volatile(
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV sp, %1 \n"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
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);
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}
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/** \brief Get FPEXC
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\return Floating Point Exception Control register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
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{
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#if (__FPU_PRESENT == 1)
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uint32_t result;
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__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
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return(result);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPEXC
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\param [in] fpexc Floating Point Exception Control value to set
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*/
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__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
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{
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#if (__FPU_PRESENT == 1)
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__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
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#endif
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}
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/** @} end of CMSIS_Core_RegAccFunctions */
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/*
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* Include common core functions to access Coprocessor 15 registers
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*/
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
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#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
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#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
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#endif /* __CMSIS_ARMCLANG_R_H */
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