392 lines
13 KiB
C
392 lines
13 KiB
C
/*
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* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File
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*/
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#ifndef __CMSIS_ARMCLANG_A_H
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#define __CMSIS_ARMCLANG_A_H
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#pragma clang system_header /* treat file as system include file */
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#ifndef __CMSIS_ARMCLANG_H
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#error "This file must not be included directly"
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#endif
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/**
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\brief STRT Unprivileged (8 bit)
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\details Executes a Unprivileged STRT instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
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{
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__ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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}
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/**
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\brief STRT Unprivileged (16 bit)
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\details Executes a Unprivileged STRT instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
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{
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__ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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}
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/**
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\brief STRT Unprivileged (32 bit)
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\details Executes a Unprivileged STRT instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
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{
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__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
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}
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/* ################### Compiler specific Intrinsics ########################### */
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/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
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Access to dedicated SIMD instructions
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@{
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*/
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#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
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#define __SADD8 __builtin_arm_sadd8
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#define __QADD8 __builtin_arm_qadd8
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#define __SHADD8 __builtin_arm_shadd8
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#define __UADD8 __builtin_arm_uadd8
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#define __UQADD8 __builtin_arm_uqadd8
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#define __UHADD8 __builtin_arm_uhadd8
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#define __SSUB8 __builtin_arm_ssub8
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#define __QSUB8 __builtin_arm_qsub8
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#define __SHSUB8 __builtin_arm_shsub8
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#define __USUB8 __builtin_arm_usub8
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#define __UQSUB8 __builtin_arm_uqsub8
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#define __UHSUB8 __builtin_arm_uhsub8
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#define __SADD16 __builtin_arm_sadd16
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#define __QADD16 __builtin_arm_qadd16
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#define __SHADD16 __builtin_arm_shadd16
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#define __UADD16 __builtin_arm_uadd16
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#define __UQADD16 __builtin_arm_uqadd16
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#define __UHADD16 __builtin_arm_uhadd16
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#define __SSUB16 __builtin_arm_ssub16
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#define __QSUB16 __builtin_arm_qsub16
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#define __SHSUB16 __builtin_arm_shsub16
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#define __USUB16 __builtin_arm_usub16
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#define __UQSUB16 __builtin_arm_uqsub16
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#define __UHSUB16 __builtin_arm_uhsub16
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#define __SASX __builtin_arm_sasx
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#define __QASX __builtin_arm_qasx
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#define __SHASX __builtin_arm_shasx
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#define __UASX __builtin_arm_uasx
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#define __UQASX __builtin_arm_uqasx
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#define __UHASX __builtin_arm_uhasx
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#define __SSAX __builtin_arm_ssax
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#define __QSAX __builtin_arm_qsax
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#define __SHSAX __builtin_arm_shsax
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#define __USAX __builtin_arm_usax
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#define __UQSAX __builtin_arm_uqsax
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#define __UHSAX __builtin_arm_uhsax
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#define __USAD8 __builtin_arm_usad8
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#define __USADA8 __builtin_arm_usada8
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#define __SSAT16 __builtin_arm_ssat16
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#define __USAT16 __builtin_arm_usat16
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#define __UXTB16 __builtin_arm_uxtb16
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#define __UXTAB16 __builtin_arm_uxtab16
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#define __SXTB16 __builtin_arm_sxtb16
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#define __SXTAB16 __builtin_arm_sxtab16
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#define __SMUAD __builtin_arm_smuad
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#define __SMUADX __builtin_arm_smuadx
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#define __SMLAD __builtin_arm_smlad
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#define __SMLADX __builtin_arm_smladx
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#define __SMLALD __builtin_arm_smlald
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#define __SMLALDX __builtin_arm_smlaldx
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#define __SMUSD __builtin_arm_smusd
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#define __SMUSDX __builtin_arm_smusdx
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#define __SMLSD __builtin_arm_smlsd
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#define __SMLSDX __builtin_arm_smlsdx
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#define __SMLSLD __builtin_arm_smlsld
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#define __SMLSLDX __builtin_arm_smlsldx
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#define __SEL __builtin_arm_sel
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#define __QADD __builtin_arm_qadd
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#define __QSUB __builtin_arm_qsub
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#define __PKHBT(ARG1,ARG2,ARG3) \
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__extension__ \
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({ \
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uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
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__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
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__RES; \
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})
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#define __PKHTB(ARG1,ARG2,ARG3) \
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__extension__ \
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({ \
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uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
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if (ARG3 == 0) \
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__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
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else \
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__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
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__RES; \
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})
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__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
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{
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uint32_t result;
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if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
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{
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__ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
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}
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else
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{
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result = __SXTB16(__ROR(op1, rotate));
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}
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return result;
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}
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__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
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{
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uint32_t result;
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if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
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{
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__ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
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}
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else
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{
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result = __SXTAB16(op1, __ROR(op2, rotate));
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}
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return result;
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}
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__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
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{
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int32_t result;
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__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
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return (result);
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}
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#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
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/** @} end of group CMSIS_SIMD_intrinsics */
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/** \brief Get CPSR Register
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\return CPSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
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{
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uint32_t result;
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__ASM volatile("MRS %0, cpsr" : "=r" (result) );
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return(result);
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}
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/** \brief Set CPSR Register
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\param [in] cpsr CPSR value to set
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*/
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__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
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{
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__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
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}
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/** \brief Get Mode
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\return Processor Mode
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*/
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__STATIC_FORCEINLINE uint32_t __get_mode(void)
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{
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return (__get_CPSR() & 0x1FU);
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}
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/** \brief Set Mode
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\param [in] mode Mode value to set
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*/
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__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
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{
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__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
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}
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/** \brief Get Stack Pointer
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\return Stack Pointer value
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*/
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__STATIC_FORCEINLINE uint32_t __get_SP(void)
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{
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uint32_t result;
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__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
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return result;
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}
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/** \brief Set Stack Pointer
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\param [in] stack Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
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{
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__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
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}
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/** \brief Get USR/SYS Stack Pointer
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\return USR/SYS Stack Pointer value
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*/
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__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
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{
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uint32_t cpsr;
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uint32_t result;
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__ASM volatile(
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV %1, sp \n"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
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);
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return result;
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}
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/** \brief Set USR/SYS Stack Pointer
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\param [in] topOfProcStack USR/SYS Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
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{
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uint32_t cpsr;
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__ASM volatile(
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"MRS %0, cpsr \n"
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"CPS #0x1F \n" // no effect in USR mode
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"MOV sp, %1 \n"
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"MSR cpsr_c, %0 \n" // no effect in USR mode
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"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
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);
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}
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/** \brief Get FPEXC
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\return Floating Point Exception Control register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
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{
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#if (__FPU_PRESENT == 1)
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uint32_t result;
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__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
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return(result);
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#else
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return(0);
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#endif
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}
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/** \brief Set FPEXC
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\param [in] fpexc Floating Point Exception Control value to set
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*/
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__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
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{
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#if (__FPU_PRESENT == 1)
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__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
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#endif
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}
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/** @} end of CMSIS_Core_RegAccFunctions */
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/*
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* Include common core functions to access Coprocessor 15 registers
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*/
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#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
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#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
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#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
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#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
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#include "cmsis_cp15.h"
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/** \brief Enable Floating Point Unit
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Critical section, called from undef handler, so systick is disabled
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*/
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__STATIC_INLINE void __FPU_Enable(void)
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{
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__ASM volatile(
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// Permit access to VFP/NEON, registers by modifying CPACR
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" MRC p15,0,R1,c1,c0,2 \n"
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" ORR R1,R1,#0x00F00000 \n"
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" MCR p15,0,R1,c1,c0,2 \n"
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// Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
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" ISB \n"
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// Enable VFP/NEON
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" VMRS R1,FPEXC \n"
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" ORR R1,R1,#0x40000000 \n"
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" VMSR FPEXC,R1 \n"
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// Initialise VFP/NEON registers to 0
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" MOV R2,#0 \n"
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// Initialise D16 registers to 0
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" VMOV D0, R2,R2 \n"
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" VMOV D1, R2,R2 \n"
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" VMOV D2, R2,R2 \n"
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" VMOV D3, R2,R2 \n"
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" VMOV D4, R2,R2 \n"
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" VMOV D5, R2,R2 \n"
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" VMOV D6, R2,R2 \n"
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" VMOV D7, R2,R2 \n"
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" VMOV D8, R2,R2 \n"
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" VMOV D9, R2,R2 \n"
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" VMOV D10,R2,R2 \n"
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" VMOV D11,R2,R2 \n"
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" VMOV D12,R2,R2 \n"
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" VMOV D13,R2,R2 \n"
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" VMOV D14,R2,R2 \n"
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" VMOV D15,R2,R2 \n"
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#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
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// Initialise D32 registers to 0
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" VMOV D16,R2,R2 \n"
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" VMOV D17,R2,R2 \n"
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" VMOV D18,R2,R2 \n"
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" VMOV D19,R2,R2 \n"
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" VMOV D20,R2,R2 \n"
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" VMOV D21,R2,R2 \n"
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" VMOV D22,R2,R2 \n"
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" VMOV D23,R2,R2 \n"
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" VMOV D24,R2,R2 \n"
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" VMOV D25,R2,R2 \n"
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" VMOV D26,R2,R2 \n"
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" VMOV D27,R2,R2 \n"
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" VMOV D28,R2,R2 \n"
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" VMOV D29,R2,R2 \n"
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" VMOV D30,R2,R2 \n"
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" VMOV D31,R2,R2 \n"
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#endif
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// Initialise FPSCR to a known state
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" VMRS R1,FPSCR \n"
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" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
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" AND R1,R1,R2 \n"
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" VMSR FPSCR,R1 "
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: : : "cc", "r1", "r2"
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);
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}
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#endif /* __CMSIS_ARMCLANG_A_H */
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